1. Field of Invention
This invention is in the general field of apparatus for measuring frequency stability of electrical signals and methods therefor and, more particularly, is an apparatus for measuring cycle to cycle jitter of a digital signal and method therefor.
2. Description of the Prior Art
A phase locked loop (PLL) is a device where a digital PLL reference signal is applied to one of two inputs of a phase detector. An output signal from a voltage controlled oscillator (VCO) of the PLL is applied to the other input of the phase detector.
The output of the VCO is a digital signal having a frequency directly related to the amplitude of an applied input voltage. The phase detector output is a signal having an amplitude proportional to the difference between the phase of the PLL reference signal and the phase of the VCO output signal.
The phase detector output usually drives an amplifier that has its output connected to the input of the VCO. Accordingly, the PLL is a feedback device where the frequency of the VCO output signal equals the frequency of the PLL reference signal. Moreover, when the frequencies are equal, the PLL is said to be locked.
It should be understood that the stability of the PLL is directly related to the phase stability of the PLL reference signal. When the phase of the PLL reference signal varies rapidly, for example, the PLL may break lock and become unstable. A system, wherein the PLL is included as a component, may fail when the PLL breaks lock.
Accordingly, it is desirable to be able to specify aspects of the PLL reference signal that effect the performance of the PLL. Additionally, it is desirable to be able to measure these aspects of the PLL reference signal.